1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly to a semiconductor memory device having memory cells storing data in capacitors.
2. Description of the Background Art
In a data processing field and the like, a circuit device called a system LSI (large-scale integrated circuit), wherein a memory device and a logic such as a processor are integrated in the same semiconductor chip, has been widely used in order to process data at a high speed with low power consumption. In the system LSI, the logic and the memory device are interconnected through on-chip interconnect lines. Therefore, the system LSI has the following advantages: (1) since the load of the signal interconnection lines is smaller than that of on-board interconnection lines, data/signals can be transmitted at a high speed; (2) since the number of pin terminals is not limited, the number of data bits can be made large so that the band width in transmitting data can be widened; (3) since the constituent elements are integrated on the semiconductor chip, the system scale can be reduced to implement a down-sized and light system, as compared to the configuration wherein discrete elements are arranged on a board; and (4) a macro prepared as a library can be arranged as a component formed on a semiconductor chip, and the efficiency of design is improved.
For the above-mentioned reasons, system LSIs are widely used in various fields. As a memory device to be integrated in the system LSI, there are used a DRAM (dynamic random access memory), an SRAM (static random access memory), and a flash type EEPROM (electrically erasable read only memory). As the logic, a processor for performing control and processing, an analogue processing circuit such as an A/D converting circuit, a logic circuit for performing a dedicated logic processing and such are used.
In the case that a processor and a memory device are integrated in a system LSI, in order to reduce the number of manufacturing steps and costs, these logic and memory device should be formed in the common manufacturing steps as long as possible. In a DRAM, data are stored in as capacitor in an electrical charge form. This capacitor has electrodes, called a cell plate electrode and a storage node electrode, on a semiconductor substrate region. The structure of this capacitor has a complicated shape, such as a hollow cylindrical shape, in order to reduce the occupancy area of the capacitor and to increase the capacitance thereof as far as possible. With a DRAM and logic mixed process for forming a DRAM and a logic in the same manufacturing steps, transistors of the logic and those of the DRAM are formed in the same manufacturing steps. However, it becomes necessary to carry out a manufacturing step for forming capacitors of the DRAM, and a flattening step for reducing a step height between the DRAM and the logic or between the memory array of the DRAM and the peripheral circuitry thereof, wherein the step height is caused based on the three-dimensional structure of the capacitors of the DRAM. Thus, problems that the number of manufacturing steps increases significantly and chip costs increases are caused.
In an SRAM, its memory cell is composed of 4 transistors and 2 load elements. These load elements are usually formed of MOS transistors (insulated gate field effect transistors), but are not formed of capacitors or the like. Therefore, the SRAM can be formed through a full CMOS logic process. That is, the SRAM and a logic can be formed in the same manufacturing steps. An SRAM has been used, for example, for a register file memory and a cache memory for a processor because of the high speed operability thereof and others.
In an SRAM, its memory cell is a flip-flop circuit. Thus, so far as a power supply voltage is supplied to the SRAM, data are held therein. Therefore, the SRAM does not require any refreshing for holding data, unlike a DRAM. Accordingly, the SRAM does not require any complicated memory control associated with the refreshing which is indispensable for the DRAM. For the SRAM, therefore, control is made simpler than for the DRAM. Thus, the SRAM is widely used as a main memory in order to simplify the system structure of a portable information terminal and such.
However, in portable information terminals, a larger quantity of data such as voice data and image data must be handled with a recent improvement in functions thereof. Thus, a memory having a large memory capacity is strongly required.
Concerning DRAM, the size thereof is being shrunk (is being miniaturized) as the miniaturizing process is being developed. For example, in a 0.18-xcexcm DRAM process, a cell size of 0.3 square xcexcm is achieved. On the other hand, in SRAMs, their full CMOS memory cell is composed of 2 P channel MOS transistors and 4 N channel MOS transistors, that is, 6 MOS transistors as a whole. Even if the shrinking process advances, it is necessary to isolate an N well for forming the P channel MOS transistors in a memory cell from a P well for forming the N channel MOS transistors thereof. Because of a restriction due to separation distance between the wells and others, the shrinking of the memory size in SRAMs advances less than in DRAM. For example, the memory size of an SRAM with a 0.18-xcexcm CMOS logic process is about 7 square xcexcm, and is about 20 times greater than the memory size of DRAM. Thus, when an SRAM is used as a main memory having a large memory capacity, the size of the chip becomes very large. Accordingly, it is very difficult to merge an SRAM having a memory capacity of 4 M bits or more with a logic in a system LSI having a restricted chip area.
An object of the present invention is to provide a semiconductor memory device having a small occupancy area and making it possible to achieve a large memory capacity without increasing the number of manufacturing steps significantly.
Another object of the present invention is to provide a semiconductor memory device which has an array configuration of a small occupancy area and can be produced with a process similar to a CMOS process.
A further object of the present invention is to provide a semiconductor memory device having a memory cell configuration which has a small occupancy area and is suitable for a CMOS production process.
A still further object of the present invention is to provide a semiconductor memory device having a memory cell configuration which has a small occupancy area and is based on DRAM cells.
A semiconductor memory device according to a first aspect of the present invention includes memory cells arranged in row and columns and each including a capacitor having a cell plate electrode receiving a reference voltage and a storage electrode for accumulating electric charges according to storage data; and word lines arranged corresponding to the rows of memory cells and each connecting to the memory cell in the corresponding row. These word lines are formed in the same interconnecting layer as the cell plate electrodes.
The semiconductor memory device according to the first aspect of the present invention further includes bit lines arranged corresponding to the columns of memory cells, and each connecting to the memory cells in the corresponding column; and a row selecting circuit for selecting an addressed word line from the word lines in accordance with an address signal. The bit lines are arranged in pairs, and the memory cells are arranged such that data in the selected memory cells are simultaneously read out onto the bit lines in a pair by a selected word line.
A semiconductor memory device according to a second aspect of the present invention includes memory cells arranged in rows and columns. Each of the memory cells includes a capacitor having a cell plate electrode receiving a reference voltage and a storage electrode for accumulating electric charges according to storage data.
The semiconductor memory device according to the second aspect of the present invention further includes word lines arranged corresponding to rows of the memory cells and each connecting to the memory cells on a corresponding row. These word lines include an interconnection line formed as the same interconnecting layer of the cell plate electrode. The cell plate electrodes and the word lines are arranged in pairs.
The semiconductor memory device according to the second aspect of the present invention further includes a cell plate voltage control circuit for changing the cell plate electrode voltage from this reference voltage level after data are read out from the memory cell in an access period of a memory cell, and returning the cell plate electrode voltage to the reference voltage level when the access cycle is completed.
A semiconductor memory device according to a third aspect of the present invention includes memory cells arranged in rows and columns. Each of the memory cells includes a capacitor having a cell plate electrode receiving a reference voltage and a storage electrode for accumulating electric charges according to storage data.
The semiconductor memory device of the third aspect of the present invention further includes word lines arranged corresponding to the rows of memory cells and each connecting to the memory cells on a corresponding row. Each of the word lines includes an interconnection line formed in an interconnection layer lower than and different from an interconnection layer of the cell plate electrodes.
The semiconductor memory device of the third aspect of the present invention further includes bit lines arranged corresponding to the columns of memory cells and each connecting to the memory cells in the corresponding column. These bit lines are formed in a layer above the word lines and the cell plate electrodes. A contact is shared between two memory cells aligned in the column direction, and the memory cells adjacent in the row direction are simultaneously connected to the corresponding bit lines. The memory cells connected to a pair of the bit lines adjacent to each other constitute a unit for storing 1-bit data.
A semiconductor memory device according to a fourth aspect of the present invention includes memory cells arranged in rows and columns. Each of the memory cells includes a capacitor having a cell plate electrode receiving a reference voltage and a storage electrode for accumulating electric charges according to storage data.
The semiconductor memory device according to the fourth aspect of the present invention further includes word lines arranged corresponding to the rows of memory cells and each connecting to the memory cells in the corresponding row. Each of the word lines includes an interconnection line formed in a lower first interconnection layer that is different from an interconnecting layer of the cell plate electrodes. The cell plate electrodes include an interconnection line formed in a second interconnection layer above the first interconnection layer.
The semiconductor memory device according to the fourth aspect of the present invention further includes bit lines arranged corresponding to the columns of memory cells and each connecting to the memory cells in the corresponding column. Each of these bit lines is formed above the word lines and the cell plate electrodes. Units composed of two memory cells are arranged with one column shifted in the column direction, and the bit lines constituting a pair sandwiches a bit line of another bit line pair. The memory cells of a unit are simultaneously connected to the corresponding bit lines of a pair, and a 1-bit data is stored in the memory cells constituting a unit.
A semiconductor memory device according to a fifth aspect of the present invention includes memory cells arranged in row and columns. Each of the memory cells includes a capacitor having a cell plate electrode receiving a reference voltage and a storage electrode for accumulating electric charges according to storage data, and the storage electrode layer is formed facing to the cell plate electrode on a surface of a semiconductor substrate region.
The semiconductor memory device according to the fifth aspect of the present invention further includes word lines arranged corresponding to the rows of memory cells and each connecting to the memory cells in the corresponding row; and a cell plate voltage control circuit for changing the voltage of the cell plate electrodes to a first reference voltage level in synchronization with the transition of a selected word line into a non-select state upon completion of an access cycle for selecting a memory cell, and changing the first reference voltage to a second reference voltage level upon starting of the access cycle.
By forming the word lines connected to the memory cell rows and the cell plate electrodes of the memory cell capacitors at the same interconnecting layer, the projection of the memory capacitors in the upper direction from the substrate can be suppressed. That is, the three-dimensional configuration of the capacitor section can be set into a parallel plate type capacitor. Thus, a step based on the memory cell capacitors can be reduced. Moreover, the word lines and the cell plate electrodes of the memory cell capacitors can be formed by the same manufacturing process. As a result, CMOS process can be used for the manufacturing process of the memory cells, and the memory cell capacitors and the word lines can be formed through the same manufacturing process as that of the logic.
Furthermore, it becomes unnecessary to use a flattening process (planarization process) step for reducing the step height between the logic and the memory. Thus, the number of the manufacturing steps can be reduced.
Additionally, by using DRAM cells as the memory cells, memory cells having a small occupancy area can be achieved. Even in the configuration in which 1-bit data is stored in two DRAM cells, the area of the memory cell unit for storing the 1-bit data can be made far smaller as compared to SRAM. Thus, a semiconductor memory device which has a small occupancy area and is suitable for merging with a logic can be achieved.
By making the word lines and the cell plate electrodes at different interconnection layers, the facing area of each of the cell plate electrodes and the corresponding storage node electrode can be made large. Consequently, the capacitance of the memory cells can be made large and a sufficiently large capacitance can be ensured against shrinking of memory cells.
By changing the cell plate voltage dependently on an operation cycle, it is possible to compensate for a change in the voltage of the storage node according to leakage current. Thus, data-holding characteristics can be improved.
By making the memory cells into the trench isolation configuration and forming the cell plate electrodes, over the insulating film, on the side walls of the trenches, the so-called isolation merged type memory cell capacitors can be realized. In memory cells subjected to shrinking, memory cell capacitors having a sufficiently large capacitance can be implemented.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.